<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.14"/>
<meta name="viewport" content="width=device-width, initial-scale=1"/>
<title>qspipsu: xqspipsu_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtreedata.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.gif"/></td>
  <td id="projectalign" style="padding-left: 0.5em;">
   <div id="projectname">qspipsu
   </div>
   <div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.14 -->
<script type="text/javascript" src="menudata.js"></script>
<script type="text/javascript" src="menu.js"></script>
<script type="text/javascript">
$(function() {
  initMenu('',false,false,'search.php','Search');
});
</script>
<div id="main-nav"></div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xqspipsu__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">xqspipsu_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga49734e127e6359b15c1ce7f117748c36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a>&#160;&#160;&#160;0XFF0F0000U</td></tr>
<tr class="memdesc:ga49734e127e6359b15c1ce7f117748c36"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Base Address.  <a href="group__qspipsu__v1__0.html#ga49734e127e6359b15c1ce7f117748c36">More...</a><br /></td></tr>
<tr class="separator:ga49734e127e6359b15c1ce7f117748c36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga137198cf9ed99131ff88af7201399ebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga137198cf9ed99131ff88af7201399ebe">XQSPIPSU_BASEADDR</a>&#160;&#160;&#160;0xFF0F0100U</td></tr>
<tr class="memdesc:ga137198cf9ed99131ff88af7201399ebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">GQSPI Base Address.  <a href="group__qspipsu__v1__0.html#ga137198cf9ed99131ff88af7201399ebe">More...</a><br /></td></tr>
<tr class="separator:ga137198cf9ed99131ff88af7201399ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab5bb698f82719c1ffdf5055dd5ebf939">XQSPIPS_EN_REG</a>&#160;&#160;&#160;( ( <a class="el" href="group__qspipsu__v1__0.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a> ) + 0X00000014U )</td></tr>
<tr class="memdesc:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPS_EN_REG.  <a href="group__qspipsu__v1__0.html#gab5bb698f82719c1ffdf5055dd5ebf939">More...</a><br /></td></tr>
<tr class="separator:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d76a2f706f3988da79345132e484303"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>&#160;&#160;&#160;0X00000000U</td></tr>
<tr class="memdesc:ga1d76a2f706f3988da79345132e484303"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="group__qspipsu__v1__0.html#ga1d76a2f706f3988da79345132e484303">More...</a><br /></td></tr>
<tr class="separator:ga1d76a2f706f3988da79345132e484303"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02a2df38913ec3616e70351637cbbb50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga02a2df38913ec3616e70351637cbbb50">XQSPIPSU_LQSPI_CR_OFFSET</a>&#160;&#160;&#160;0X000000A0U</td></tr>
<tr class="memdesc:ga02a2df38913ec3616e70351637cbbb50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="group__qspipsu__v1__0.html#ga02a2df38913ec3616e70351637cbbb50">More...</a><br /></td></tr>
<tr class="separator:ga02a2df38913ec3616e70351637cbbb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02a2df38913ec3616e70351637cbbb50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga02a2df38913ec3616e70351637cbbb50">XQSPIPSU_LQSPI_CR_OFFSET</a>&#160;&#160;&#160;0X000000A0U</td></tr>
<tr class="memdesc:ga02a2df38913ec3616e70351637cbbb50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="group__qspipsu__v1__0.html#ga02a2df38913ec3616e70351637cbbb50">More...</a><br /></td></tr>
<tr class="separator:ga02a2df38913ec3616e70351637cbbb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5bfff58ddca187becec7c533cf355fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gac5bfff58ddca187becec7c533cf355fe">XQSPIPSU_LQSPI_CR_LINEAR_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gac5bfff58ddca187becec7c533cf355fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">LQSPI mode enable.  <a href="group__qspipsu__v1__0.html#gac5bfff58ddca187becec7c533cf355fe">More...</a><br /></td></tr>
<tr class="separator:gac5bfff58ddca187becec7c533cf355fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga6fbc52b88d443b2a5ea258ff83ef71f2">XQSPIPSU_LQSPI_CR_TWO_MEM_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both memories or one.  <a href="group__qspipsu__v1__0.html#ga6fbc52b88d443b2a5ea258ff83ef71f2">More...</a><br /></td></tr>
<tr class="separator:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66a4736f3e48910c8ba8dc2999b16558"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga66a4736f3e48910c8ba8dc2999b16558">XQSPIPSU_LQSPI_CR_SEP_BUS_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga66a4736f3e48910c8ba8dc2999b16558"><td class="mdescLeft">&#160;</td><td class="mdescRight">Seperate memory bus.  <a href="group__qspipsu__v1__0.html#ga66a4736f3e48910c8ba8dc2999b16558">More...</a><br /></td></tr>
<tr class="separator:ga66a4736f3e48910c8ba8dc2999b16558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaa7502d70b7ddd899d5bf8bba3f23d70e">XQSPIPSU_LQSPI_CR_U_PAGE_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="group__qspipsu__v1__0.html#gaa7502d70b7ddd899d5bf8bba3f23d70e">More...</a><br /></td></tr>
<tr class="separator:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5406192835c4f1d618b56626790628b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5406192835c4f1d618b56626790628b1">XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:ga5406192835c4f1d618b56626790628b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="group__qspipsu__v1__0.html#ga5406192835c4f1d618b56626790628b1">More...</a><br /></td></tr>
<tr class="separator:ga5406192835c4f1d618b56626790628b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0eecbc04289c520b605393012c8715ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga0eecbc04289c520b605393012c8715ff">XQSPIPSU_LQSPI_CR_MODE_EN_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:ga0eecbc04289c520b605393012c8715ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable mode bits.  <a href="group__qspipsu__v1__0.html#ga0eecbc04289c520b605393012c8715ff">More...</a><br /></td></tr>
<tr class="separator:ga0eecbc04289c520b605393012c8715ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40238108ef1f0763edaf8adc59c03d72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga40238108ef1f0763edaf8adc59c03d72">XQSPIPSU_LQSPI_CR_MODE_ON_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:ga40238108ef1f0763edaf8adc59c03d72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode on.  <a href="group__qspipsu__v1__0.html#ga40238108ef1f0763edaf8adc59c03d72">More...</a><br /></td></tr>
<tr class="separator:ga40238108ef1f0763edaf8adc59c03d72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3cd6ea3b67401b777b26365937e9c97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad3cd6ea3b67401b777b26365937e9c97">XQSPIPSU_LQSPI_CR_MODE_BITS_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gad3cd6ea3b67401b777b26365937e9c97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode value for dual I/O or quad I/O.  <a href="group__qspipsu__v1__0.html#gad3cd6ea3b67401b777b26365937e9c97">More...</a><br /></td></tr>
<tr class="separator:gad3cd6ea3b67401b777b26365937e9c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad327ae631cb6e447615bc9534738af72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad327ae631cb6e447615bc9534738af72">XQSPIPS_LQSPI_CR_INST_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:gad327ae631cb6e447615bc9534738af72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read instr code.  <a href="group__qspipsu__v1__0.html#gad327ae631cb6e447615bc9534738af72">More...</a><br /></td></tr>
<tr class="separator:gad327ae631cb6e447615bc9534738af72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f187c067994aa193d43051cb5fef0db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga6f187c067994aa193d43051cb5fef0db">XQSPIPS_LQSPI_CR_RST_STATE</a>&#160;&#160;&#160;0x80000003</td></tr>
<tr class="memdesc:ga6f187c067994aa193d43051cb5fef0db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default LQSPI CR value.  <a href="group__qspipsu__v1__0.html#ga6f187c067994aa193d43051cb5fef0db">More...</a><br /></td></tr>
<tr class="separator:ga6f187c067994aa193d43051cb5fef0db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c05a7421b8aea31df3d026189282cce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3c05a7421b8aea31df3d026189282cce">XQSPIPS_LQSPI_CFG_RST_STATE</a>&#160;&#160;&#160;0x800238C1</td></tr>
<tr class="memdesc:ga3c05a7421b8aea31df3d026189282cce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default LQSPI CFG value.  <a href="group__qspipsu__v1__0.html#ga3c05a7421b8aea31df3d026189282cce">More...</a><br /></td></tr>
<tr class="separator:ga3c05a7421b8aea31df3d026189282cce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadae24d033fb12577e3e4eda5427a950a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gadae24d033fb12577e3e4eda5427a950a">XQSPIPSU_ISR_OFFSET</a>&#160;&#160;&#160;0X00000004U</td></tr>
<tr class="memdesc:gadae24d033fb12577e3e4eda5427a950a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_ISR.  <a href="group__qspipsu__v1__0.html#gadae24d033fb12577e3e4eda5427a950a">More...</a><br /></td></tr>
<tr class="separator:gadae24d033fb12577e3e4eda5427a950a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab8e3a4621239cb556fc8acdd0a6d10b6">XQSPIPSU_IER_OFFSET</a>&#160;&#160;&#160;0X00000008U</td></tr>
<tr class="memdesc:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IER.  <a href="group__qspipsu__v1__0.html#gab8e3a4621239cb556fc8acdd0a6d10b6">More...</a><br /></td></tr>
<tr class="separator:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5eb684785dfb0a249b18126089624b91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5eb684785dfb0a249b18126089624b91">XQSPIPSU_IDR_OFFSET</a>&#160;&#160;&#160;0X0000000CU</td></tr>
<tr class="memdesc:ga5eb684785dfb0a249b18126089624b91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IDR.  <a href="group__qspipsu__v1__0.html#ga5eb684785dfb0a249b18126089624b91">More...</a><br /></td></tr>
<tr class="separator:ga5eb684785dfb0a249b18126089624b91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1711ff533a11dd37b3d72056050025e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga1711ff533a11dd37b3d72056050025e5">XQSPIPSU_IMR_OFFSET</a>&#160;&#160;&#160;0X00000010U</td></tr>
<tr class="memdesc:ga1711ff533a11dd37b3d72056050025e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IMR.  <a href="group__qspipsu__v1__0.html#ga1711ff533a11dd37b3d72056050025e5">More...</a><br /></td></tr>
<tr class="separator:ga1711ff533a11dd37b3d72056050025e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">XQSPIPSU_EN_OFFSET</a>&#160;&#160;&#160;0X00000014U</td></tr>
<tr class="memdesc:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_EN_REG.  <a href="group__qspipsu__v1__0.html#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">More...</a><br /></td></tr>
<tr class="separator:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4884f0160746c6696598ef6dda1fc9ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4884f0160746c6696598ef6dda1fc9ff">XQSPIPSU_TXD_OFFSET</a>&#160;&#160;&#160;0X0000001CU</td></tr>
<tr class="memdesc:ga4884f0160746c6696598ef6dda1fc9ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_TXD.  <a href="group__qspipsu__v1__0.html#ga4884f0160746c6696598ef6dda1fc9ff">More...</a><br /></td></tr>
<tr class="separator:ga4884f0160746c6696598ef6dda1fc9ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68b0b4316693414546980dea7baaf0a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga68b0b4316693414546980dea7baaf0a4">XQSPIPSU_RXD_OFFSET</a>&#160;&#160;&#160;0X00000020U</td></tr>
<tr class="memdesc:ga68b0b4316693414546980dea7baaf0a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RXD.  <a href="group__qspipsu__v1__0.html#ga68b0b4316693414546980dea7baaf0a4">More...</a><br /></td></tr>
<tr class="separator:ga68b0b4316693414546980dea7baaf0a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33bc760357127168b3a665f969036421"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga33bc760357127168b3a665f969036421">XQSPIPSU_TX_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X00000028U</td></tr>
<tr class="memdesc:ga33bc760357127168b3a665f969036421"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_TX_THRESHOLD.  <a href="group__qspipsu__v1__0.html#ga33bc760357127168b3a665f969036421">More...</a><br /></td></tr>
<tr class="separator:ga33bc760357127168b3a665f969036421"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97be55c27b71a154877fb5f919d627f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga97be55c27b71a154877fb5f919d627f1">XQSPIPSU_RX_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X0000002CU</td></tr>
<tr class="memdesc:ga97be55c27b71a154877fb5f919d627f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RX_THRESHOLD.  <a href="group__qspipsu__v1__0.html#ga97be55c27b71a154877fb5f919d627f1">More...</a><br /></td></tr>
<tr class="separator:ga97be55c27b71a154877fb5f919d627f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad50a54ee932051b2fed093ef6f2e8a12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad50a54ee932051b2fed093ef6f2e8a12">XQSPIPSU_GPIO_OFFSET</a>&#160;&#160;&#160;0X00000030U</td></tr>
<tr class="memdesc:gad50a54ee932051b2fed093ef6f2e8a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GPIO.  <a href="group__qspipsu__v1__0.html#gad50a54ee932051b2fed093ef6f2e8a12">More...</a><br /></td></tr>
<tr class="separator:gad50a54ee932051b2fed093ef6f2e8a12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4636d144794bb35424cacd6f6d49781a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4636d144794bb35424cacd6f6d49781a">XQSPIPSU_LPBK_DLY_ADJ_OFFSET</a>&#160;&#160;&#160;0X00000038U</td></tr>
<tr class="memdesc:ga4636d144794bb35424cacd6f6d49781a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_LPBK_DLY_ADJ.  <a href="group__qspipsu__v1__0.html#ga4636d144794bb35424cacd6f6d49781a">More...</a><br /></td></tr>
<tr class="separator:ga4636d144794bb35424cacd6f6d49781a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3bfe2023b6a6ce56e9d13f130bd1c86d">XQSPIPSU_GEN_FIFO_OFFSET</a>&#160;&#160;&#160;0X00000040U</td></tr>
<tr class="memdesc:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GEN_FIFO.  <a href="group__qspipsu__v1__0.html#ga3bfe2023b6a6ce56e9d13f130bd1c86d">More...</a><br /></td></tr>
<tr class="separator:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84156abbc51d17b988b1e82c584be10d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga84156abbc51d17b988b1e82c584be10d">XQSPIPSU_SEL_OFFSET</a>&#160;&#160;&#160;0X00000044U</td></tr>
<tr class="memdesc:ga84156abbc51d17b988b1e82c584be10d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_SEL.  <a href="group__qspipsu__v1__0.html#ga84156abbc51d17b988b1e82c584be10d">More...</a><br /></td></tr>
<tr class="separator:ga84156abbc51d17b988b1e82c584be10d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gac14f429fa7d15b5c4bf2808ed08e7120">XQSPIPSU_FIFO_CTRL_OFFSET</a>&#160;&#160;&#160;0X0000004CU</td></tr>
<tr class="memdesc:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_FIFO_CTRL.  <a href="group__qspipsu__v1__0.html#gac14f429fa7d15b5c4bf2808ed08e7120">More...</a><br /></td></tr>
<tr class="separator:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a8034417fd3c9846c968679c1cad859"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga5a8034417fd3c9846c968679c1cad859">XQSPIPSU_GF_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X00000050U</td></tr>
<tr class="memdesc:ga5a8034417fd3c9846c968679c1cad859"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GF_THRESHOLD.  <a href="group__qspipsu__v1__0.html#ga5a8034417fd3c9846c968679c1cad859">More...</a><br /></td></tr>
<tr class="separator:ga5a8034417fd3c9846c968679c1cad859"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaf657fc3a38e22e512c0f7cf03bda1ad7">XQSPIPSU_POLL_CFG_OFFSET</a>&#160;&#160;&#160;0X00000054U</td></tr>
<tr class="memdesc:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_POLL_CFG.  <a href="group__qspipsu__v1__0.html#gaf657fc3a38e22e512c0f7cf03bda1ad7">More...</a><br /></td></tr>
<tr class="separator:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga311de6f25e5cf64057e9ba429cf86507"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga311de6f25e5cf64057e9ba429cf86507">XQSPIPSU_P_TO_OFFSET</a>&#160;&#160;&#160;0X00000058U</td></tr>
<tr class="memdesc:ga311de6f25e5cf64057e9ba429cf86507"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_P_TIMEOUT.  <a href="group__qspipsu__v1__0.html#ga311de6f25e5cf64057e9ba429cf86507">More...</a><br /></td></tr>
<tr class="separator:ga311de6f25e5cf64057e9ba429cf86507"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4951a0b7d9ce35780f74864a196092e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4951a0b7d9ce35780f74864a196092e4">XQSPIPSU_XFER_STS_OFFSET</a>&#160;&#160;&#160;0X0000005CU</td></tr>
<tr class="memdesc:ga4951a0b7d9ce35780f74864a196092e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_XFER_STS.  <a href="group__qspipsu__v1__0.html#ga4951a0b7d9ce35780f74864a196092e4">More...</a><br /></td></tr>
<tr class="separator:ga4951a0b7d9ce35780f74864a196092e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadda8c30c269feb26bc40f588da2c6097"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gadda8c30c269feb26bc40f588da2c6097">XQSPIPSU_GF_SNAPSHOT_OFFSET</a>&#160;&#160;&#160;0X00000060U</td></tr>
<tr class="memdesc:gadda8c30c269feb26bc40f588da2c6097"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GF_SNAPSHOT.  <a href="group__qspipsu__v1__0.html#gadda8c30c269feb26bc40f588da2c6097">More...</a><br /></td></tr>
<tr class="separator:gadda8c30c269feb26bc40f588da2c6097"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga419ba63e8028ea7e8aa833523ea3a785"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga419ba63e8028ea7e8aa833523ea3a785">XQSPIPSU_RX_COPY_OFFSET</a>&#160;&#160;&#160;0X00000064U</td></tr>
<tr class="memdesc:ga419ba63e8028ea7e8aa833523ea3a785"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RX_COPY.  <a href="group__qspipsu__v1__0.html#ga419ba63e8028ea7e8aa833523ea3a785">More...</a><br /></td></tr>
<tr class="separator:ga419ba63e8028ea7e8aa833523ea3a785"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9dae139fcca838438b3e14f4306f1f06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga9dae139fcca838438b3e14f4306f1f06">XQSPIPSU_MOD_ID_OFFSET</a>&#160;&#160;&#160;0X000000FCU</td></tr>
<tr class="memdesc:ga9dae139fcca838438b3e14f4306f1f06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_MOD_ID.  <a href="group__qspipsu__v1__0.html#ga9dae139fcca838438b3e14f4306f1f06">More...</a><br /></td></tr>
<tr class="separator:ga9dae139fcca838438b3e14f4306f1f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b9c82ef758ea9e8bfda707130051091"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga3b9c82ef758ea9e8bfda707130051091">XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET</a>&#160;&#160;&#160;0X00000700U</td></tr>
<tr class="memdesc:ga3b9c82ef758ea9e8bfda707130051091"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_ADDR.  <a href="group__qspipsu__v1__0.html#ga3b9c82ef758ea9e8bfda707130051091">More...</a><br /></td></tr>
<tr class="separator:ga3b9c82ef758ea9e8bfda707130051091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2dea188a0404d6e555c4ff2839eb86a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab2dea188a0404d6e555c4ff2839eb86a">XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET</a>&#160;&#160;&#160;0X00000704U</td></tr>
<tr class="memdesc:gab2dea188a0404d6e555c4ff2839eb86a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_SIZE.  <a href="group__qspipsu__v1__0.html#gab2dea188a0404d6e555c4ff2839eb86a">More...</a><br /></td></tr>
<tr class="separator:gab2dea188a0404d6e555c4ff2839eb86a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8fd8100c320c3da46a93af5adf6592f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga8fd8100c320c3da46a93af5adf6592f0">XQSPIPSU_QSPIDMA_DST_STS_OFFSET</a>&#160;&#160;&#160;0X00000708U</td></tr>
<tr class="memdesc:ga8fd8100c320c3da46a93af5adf6592f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_STS.  <a href="group__qspipsu__v1__0.html#ga8fd8100c320c3da46a93af5adf6592f0">More...</a><br /></td></tr>
<tr class="separator:ga8fd8100c320c3da46a93af5adf6592f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga1c49b7d688c394b3bb37d4293fa34df5">XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET</a>&#160;&#160;&#160;0X0000070CU</td></tr>
<tr class="memdesc:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_CTRL.  <a href="group__qspipsu__v1__0.html#ga1c49b7d688c394b3bb37d4293fa34df5">More...</a><br /></td></tr>
<tr class="separator:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fcb2a02499c783baa52e6dbba23e228"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga7fcb2a02499c783baa52e6dbba23e228">XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET</a>&#160;&#160;&#160;0X00000714U</td></tr>
<tr class="memdesc:ga7fcb2a02499c783baa52e6dbba23e228"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_I_STS.  <a href="group__qspipsu__v1__0.html#ga7fcb2a02499c783baa52e6dbba23e228">More...</a><br /></td></tr>
<tr class="separator:ga7fcb2a02499c783baa52e6dbba23e228"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaceea2425458ac2a40305f93e496865a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gaceea2425458ac2a40305f93e496865a9">XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET</a>&#160;&#160;&#160;0X00000718U</td></tr>
<tr class="memdesc:gaceea2425458ac2a40305f93e496865a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_I_EN.  <a href="group__qspipsu__v1__0.html#gaceea2425458ac2a40305f93e496865a9">More...</a><br /></td></tr>
<tr class="separator:gaceea2425458ac2a40305f93e496865a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04b009825df34055ec8a92ac44e651fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga04b009825df34055ec8a92ac44e651fa">XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET</a>&#160;&#160;&#160;0X0000071CU</td></tr>
<tr class="memdesc:ga04b009825df34055ec8a92ac44e651fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_I_DIS.  <a href="group__qspipsu__v1__0.html#ga04b009825df34055ec8a92ac44e651fa">More...</a><br /></td></tr>
<tr class="separator:ga04b009825df34055ec8a92ac44e651fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30ca967a9288020ef44470e6f09c2b6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga30ca967a9288020ef44470e6f09c2b6b">XQSPIPSU_QSPIDMA_DST_IMR_OFFSET</a>&#160;&#160;&#160;0X00000720U</td></tr>
<tr class="memdesc:ga30ca967a9288020ef44470e6f09c2b6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_IMR.  <a href="group__qspipsu__v1__0.html#ga30ca967a9288020ef44470e6f09c2b6b">More...</a><br /></td></tr>
<tr class="separator:ga30ca967a9288020ef44470e6f09c2b6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad11e1e53c55440afa41685846b74c9c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gad11e1e53c55440afa41685846b74c9c7">XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET</a>&#160;&#160;&#160;0X00000724U</td></tr>
<tr class="memdesc:gad11e1e53c55440afa41685846b74c9c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_CTRL2.  <a href="group__qspipsu__v1__0.html#gad11e1e53c55440afa41685846b74c9c7">More...</a><br /></td></tr>
<tr class="separator:gad11e1e53c55440afa41685846b74c9c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39b0151b1cd09cb2da8d67efeb8ec0cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga39b0151b1cd09cb2da8d67efeb8ec0cb">XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET</a>&#160;&#160;&#160;0X00000728U</td></tr>
<tr class="memdesc:ga39b0151b1cd09cb2da8d67efeb8ec0cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB.  <a href="group__qspipsu__v1__0.html#ga39b0151b1cd09cb2da8d67efeb8ec0cb">More...</a><br /></td></tr>
<tr class="separator:ga39b0151b1cd09cb2da8d67efeb8ec0cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4332dd0868d1843ae3a49d74844d2a8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga4332dd0868d1843ae3a49d74844d2a8f">XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET</a>&#160;&#160;&#160;0X00000EFCU</td></tr>
<tr class="memdesc:ga4332dd0868d1843ae3a49d74844d2a8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_FUTURE_ECO.  <a href="group__qspipsu__v1__0.html#ga4332dd0868d1843ae3a49d74844d2a8f">More...</a><br /></td></tr>
<tr class="separator:ga4332dd0868d1843ae3a49d74844d2a8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XQspiPsu_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group__qspipsu__v1__0.html#gab88bcdb0f53b21b79cd0805cfd14cb89">More...</a><br /></td></tr>
<tr class="separator:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga584ee0482b95d3f49353438ca58fb180"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__v1__0.html#ga584ee0482b95d3f49353438ca58fb180">XQspiPsu_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga584ee0482b95d3f49353438ca58fb180"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group__qspipsu__v1__0.html#ga584ee0482b95d3f49353438ca58fb180">More...</a><br /></td></tr>
<tr class="separator:ga584ee0482b95d3f49353438ca58fb180"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
  <ul>
    <li class="footer">Copyright &copy; 2015 Xilinx Inc. All rights reserved.</li>
  </ul>
</div>
</body>
</html>
